The present invention generally relates to integrated circuits, and more particularly, to a charge pump.
Integrated circuits (ICs) such as system-on-chips (SoCs) and application specific integrated circuits (ASICs) include various analog and digital circuits such as phase-locked loops (PLLs), delay-locked loops (DLLs), analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and memories. These circuits require different supply voltages, so an IC that receives a single power supply voltage often includes a charge pump. The charge pump is a voltage converter that includes capacitors to store and transfer energy. The charge pump receives an input supply voltage and generates an output voltage signal at a voltage level that is different from the voltage level of the input supply voltage.
FIG. 1 is a schematic block diagram of a conventional charge pump 100. The charge pump 100 receives a supply voltage (VDD) and generates an output signal (VOUT). The charge pump 100 includes an automatic pumping current control circuit 102 and an automatic frequency control circuit 104. The automatic pumping current control circuit 102 includes a first buffer 106, a main charge pump circuit 108, a buffer circuit 110, and a voltage detector 112. The main charge pump circuit 108 includes first through third transistors 114-118, and first and second capacitors 120 and 122. The buffer circuit 110 includes second through fifth buffers 124-130. The voltage detector 112 includes a voltage reference circuit 132, first through fourth resistors 134-140, and first through third comparators 142-146. The automatic frequency control circuit 104 includes a fourth comparator 148, a voltage-controlled oscillator (VCO) 150, and a fifth resistor 152. The charge pump 100 is further connected to a third capacitor 154 and a sixth resistor 156.
The voltage detector 112 receives the output signal and generates a voltage detection signal (VDET) indicative of a voltage level of the output signal. The resistors 134-138 scale the voltage level of the output signal and generate first through third voltage signals (V1, V2, and V3). The voltage reference circuit 132 generates a reference voltage (VREF). The first comparator 142 compares the reference voltage VREF with the first voltage signal V1 and generates a first comparison signal (VCOMP1). The second comparator 144 compares the reference voltage VREF with the second voltage signal V2 and generates a second comparison signal (VCOMP2). The third comparator 146 compares the reference voltage VREF with the third voltage signal V3 and generates a third comparison signal (VCOMP3). The fourth comparator 148 receives the voltage reference signal from the voltage reference circuit 132, and the voltage detection signal from the fourth resistor 140, compares them, and generates a fourth comparison signal (VCOMP4).
The VCO 150 receives the fourth comparison signal and generates an oscillating signal (VOSC). The first buffer 106 is connected to the VCO 150 and receives the oscillating signal and provides a buffered signal (VBUF). The fifth resistor 152 is connected to the fourth resistor 140 for receiving the voltage detection signal, and to ground.
The second buffer 124 is connected to the output of the first buffer 106, receives the buffered signal, and generates a first current signal (I1). The third buffer 126 receives the buffered signal from the first buffer 106; the third buffer also has a control terminal connected to the output of the first comparator 142 for receiving the first comparison signal. Based on the first comparison signal, the third buffer 126 generates a second current signal (I2). The fourth buffer 128 is connected to the output of the first buffer 106 and receives the buffered signal, and has a control terminal connected to the output of the second comparator 144 for receiving the second comparison signal. Based on the second comparison signal, the fourth buffer 128 generates a third current signal (I3). The fifth buffer 130 is connected to the output of the first buffer 106 for receiving the buffered signal and has a control terminal connected to the output of the third comparator 146 for receiving the third comparison signal. Based on the third comparison signal, the fifth buffer 130 generates a fourth current signal (I4).
The first transistor 114 has a source that receives the supply voltage and a gate connected to its drain, so the first transistor 114 functions as a diode. The second transistor 116 has a source that receives the supply voltage and a gate connected to its drain so that it too functions as a diode. The third transistor 118 has its source connected to the drain of the second transistor 116, its gate connected to the drain of the first transistor 114, and its drain generates the output signal.
The first and second capacitors 120 and 122 are connected to the drains of the first and second transistors 114 and 116, respectively. The first capacitor 120 also is connected to the output of the first buffer 106 for receiving the buffered signal, while the second capacitor 122 also is connected to the outputs of the second through fifth buffers 124-130.
The VCO 150 varies a frequency of the oscillating signal based on the fourth comparison signal. Thus, the automatic frequency control circuit 104 controls a frequency of the oscillating signal, which controls the charging rate of the second capacitor 122.
The buffer circuit 110 provides current to the second capacitor 122 by adjusting the current supplied to the second capacitor 122 based on the first through third comparison signals. When the voltage level of the output signal is less than a threshold voltage, the buffer circuit 110 uses the second through fifth buffers 124-130 for supplying maximum current to the second capacitor 122. As the voltage level of the output signal rises, the buffer circuit 110 step-wise reduces the current supplied to the second capacitor 122 to a current level of the first current signal.
Thus, the charge pump 100 controls the charging rate of the second capacitor 122, thereby regulating the voltage level of the output signal and reducing ripples introduced in the output signal. The third capacitor 154 further reduces ripples in the output signal supplied to the sixth resistor 156, which acts as a load. Thus, the charge pump 100 regulates the voltage level of the output signal based on the load variation.
However, the charge pump 100 requires four comparators, which increases its circuit area. Further, the charge pump 100 step-wise changes the current supplied to the second capacitor 122 depending on the voltage level of the output signal. Hence, the charge pump 100 reduces the ripples in the output signal in discrete steps. Further, a size of the third capacitor 154 required to reduce high frequency ripples is large, which further increases the circuit area.
Other known techniques for reducing ripples in the output signal utilize an external clock source that generates an oscillating signal at a constant frequency and hence, require complex circuits that increase both area and power.
Therefore, it would be advantageous to have a charge pump that reduces ripples in an output signal thereof and has reduced area and power.